搜索资源列表
一些VHDL源代码
- 内有波形发生器,加法器,经典双进程状态机,伪随机熟产生器,相应加法器的测试向量,16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
jop_rom
- JOP的RAM VHDL源码,经典的经典,不易找到的好东东,-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
CapacityRAMModel
- Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
dualportRAM
- 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件,完全的代码在ALTERA的FPGA上已经通过仿真测试,保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
ram
- VHDL 编写的RAM例子
ram
- fpga中ram的vhdl的经典程序,适用于ALTERA公司器件
VHDL
- 注1: 含有不可综合语句,请自行修改 注2: 一些PLD只允许I/O口对外三态,不支持内部三态,使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件,并在VHDL程序中例化
VHDL-ram_fifo
- VHDL的ram和fifo model code 包含众多的厂家
VGA图像显示
- 该项目能将RAM或ROM存储器中储存的十六进制数据显示在VGA显示器上,使用VerilogHDL]语言,在Altera的QuartusII下编译通过。
自动售货机VHDL程序与仿真
- library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_auto1 is port ( clk:in std_logic; --系统时钟 set,get,sel,finish: in std_logic; --设定、买
VHDL语言实现的arm内核
- 5个ram核,arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核,verilog写的,有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心,结构良好,简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目,国防科技大学牛人ShengYu Shen写的,原来放在opencores上,
ssram
- 同步静态RAM读写程序,可用作模块,已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
mem_ctrl_latest.tar
- 存储器控制FPGA程序,包括ram,fifo,sdram,flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
ram_tb
- ram vhdl module for modelsim and vhdl design
shishi
- 基于FPGA的实时采样系统设计!双口ram典型应用!-FPGA-based real-time sampling system!
doc
- BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional
CU-RAM-CODES
- CU RAM VHDL codes for spartan 3E board
用vhdl写实用96例子
- 用vhdl写实用96例子, 有RAM,PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
75_RAM
- fpga中对RAM的VHDL程序,非常之实用(FPGA in the RAM VHDL procedures, very practical)